HYB39S128400FTL - 128-MBit Synchronous DRAM
The HY[B/I]39S128[40/80/16][0/7]F[E/T](L) are four bank Synchronous DRAM’s organized as 32 MBit x4, 16 MBit x8 and 8 Mbit x16 respectively.
These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then sync
October 2007 www.DataSheet4U.com HYB39S128400F[E/T](L) HY[B/I]39S128800F[E/T](L) HY[B/I]39S128160F[E/T](L) HYB39S 128407 F E 128-MBit Synchronous DRAM Green Product SDRAM Data Sheet Rev.
1.32 Data Sheet www.DataSheet4U.com HY[B/I]39S128[40/80/16][0/7]F[E/T](L) 128-MBit Synchronous DRAM HYB39S128400F[E/T](L), HY[B/I]39S128800F[E/T](L), HY[B/I]39S128160F[E/T](L) Revision History: 2007-10, Rev.
1.32 Page All 23 13 15 19 19 22 22 15 21 22 4 Subjects (major changes since last revision) Adapted I
HYB39S128400FTL Features
* Data Mask for Read / Write control (x4, x8) Data Mask for Byte Control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 μs) Random Column Address eve
