* Auto Refresh (CBR) and Self Refresh
* Average Refresh Period 7.8 µs at a TCASE lower than 85 °C, 3.9µs between 85 °C and 95 °C.
* All inputs and outputs SSTL_1.8 compatible
* Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT)
* Serial Pr
HYS72T256023HR-5-A Datasheet (2.08 MB)
HYS72T256023HR-5-A
Qimonda
2.08 MB
240-pin registered ddr2 sdram modules.
January 2007
www.DataSheet4U.com
HYS72T256023HR
*5
*A HYS72T 512022 H R
* 3 S
* A HYS72T512022HR
*3.7
*A HY.
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