8SLVD1212 Datasheet - Renesas

8SLVD1212 LVDS fanout buffer

The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew ch.

8SLVD1212 Features

* ▪ Twelve low skew, low additive jitter LVDS output pairs ▪ Two selectable, differential clock input pairs ▪ Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL, CML ▪ Maximum input clock frequency: 2GHz (maximum) ▪ LVCMOS/LVTTL interface levels for the con

8SLVD1212-Renesas.pdf