Description
7
4. Principles Of Operation
.
10 4.2 Phase-Locked Loop Operation
Features
- High-performance clock RF sampling clock generator and clock jitter attenuator with support for JESD204B/C.
- Low phase noise: -144.7dBc/Hz (800kHz offset; 491.52MHz).
- Integrated phase noise of 74fs RMS (12k-20MHz, 491.52MHz).
- Dual-PLL architecture with internal and optional external VCO.
- Eight output channels with a total of 18 outputs.
- Configurable integer clock frequency dividers.
- Clock output frequencies: up to 3932.16MHz
(Internal VCO) and 6GHz (optional.
8V19N880-Renesas.pdf
