* gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift / load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data in
HD74LS166AP Datasheet (212.04 KB)
HD74LS166AP
212.04 KB
8-bit shift register.
HD74LS166A 8-bit Shift Register REJ03D0450-0400 Rev.4.00 May 10, 2006 The inputs are buffered to lower the drive requirements to one series 74 or 7.
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