Part number:
HD74LS107A
Manufacturer:
File Size:
195.96 KB
Description:
Dual j-k negative-edge-triggered flip-flops.
HD74LS107A Datasheet (195.96 KB)
* Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS107AP DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74LS107AFPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP Note: Please consult the sales office for the above package availability.
HD74LS107A Datasheet (195.96 KB)
HD74LS107A
195.96 KB
Dual j-k negative-edge-triggered flip-flops.
📁 Related Datasheet
HD74LS107A - Dual J-K Negative-edge-triggered Flip-Flops
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
HD74LS107AP - Dual J-K Negative-edge-triggered Flip-Flops
(Renesas)
HD74LS107A
Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
REJ03D0425–0300 Rev.3.00
Jul.13.2005
Features
• Ordering Information
Part Name
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HD74LS10 - Triple 3-input Positive NAND Gates
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
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7 7.62
0.51 Min
2.54 Min 5.06 Max
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0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
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HD74LS109 - Dual J-K Positive-edge-triggered Flip-Flops
(Hitachi Semiconductor)
19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
Hit.
HD74LS109A - Dual J-K Positive-edge-triggered Flip-Flops
(Hitachi Semiconductor)
19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
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Package Abbreviat.
HD74LS11 - Triple 3-input Positive AND Gates
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
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