* Ordering Information
* HD74LS11 Part Name Package Type HD74LS11P DILP-14 pin HD74LS11FPEL SOP-14 pin (JEITA) Package Code (Previous Code) PRDP0014AB-B (DP-14AV) PRSP0014DF-B (FP-14DAV) Package Abbreviation P FP Taping Abbreviation (Quantity)
* EL (2,000 pcs/reel)
HD74LS11P Datasheet (97.84 KB)
HD74LS11P
97.84 KB
Triple 3-input positive and gates.
HD74LS11 / HD74LS15
Triple 3-input Positive AND Gates / Triple 3-input Positive AND Gates (with Open Collector Outputs)
REJ03D0397
*0300 Rev.3..
📁 Related Datasheet
HD74LS11 - Triple 3-input Positive AND Gates
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
HD74LS11 - Triple 3-input Positive AND Gates
(Renesas)
HD74LS11 / HD74LS15
Triple 3-input Positive AND Gates / Triple 3-input Positive AND Gates (with Open Collector Outputs)
REJ03D0397–0300 Rev.3.00
Jul.1.
HD74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
(Hitachi Semiconductor)
19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
Hit.
HD74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
(Renesas)
HD74LS112
Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)
REJ03D0426–0300 Rev.3.00
Jul.13.2005
Features
• Ordering Information
P.
HD74LS112P - Dual J-K Negative-edge-triggered Flip-Flops
(Renesas)
HD74LS112
Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)
REJ03D0426–0300 Rev.3.00
Jul.13.2005
Features
• Ordering Information
P.
HD74LS113 - Dual J-K Negative-edge-triggered Flip-Flops
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
HD74LS114 - Dual J-K Negative-edge-triggered Flip-Flops
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
HD74LS10 - Triple 3-input Positive NAND Gates
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
