parallel inputs, parallel outputs, J-K serial inputs, shift / load control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of operation:.
Parallel (broadside) load.
Shift (in the direction QA toward QD)
Parallel loading is accomplished by applying the four bits of data and taking the shift / load control input low. The data is loaded into the associated flip-flop and appears at the outputs after t.