parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register has three mode operation:.
Parallel (broadside) load.
Shift right (the direction QA toward QD).
Shift left (the direction QD toward QA)
Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. Dur.