IDT2309A Datasheet - Renesas

IDT2309A 3.3V ZERO DELAY CLOCK BUFFER

The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A is a 16-pin vers.

IDT2309A Features

* Phase-Lock Loop Clock Distribution

* 10MHz to 133MHz operating frequency

* Distributes one clock input to one bank of five and one bank of four outputs

* Separate output enable for each output bank

* Output Skew < 250ps

* Low jitter

IDT2309A-Renesas.pdf