Description
The IDT72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow.
Flexible x36/x18/x9 Bus-Matching on both read and write ports
The period required by the retransmit operation is fixed and short.
Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
empty FIFO to the time it can be read,
Features
- Choose among the following memory organizations: IDT72V36100 ⎯ 65,536 x 36 IDT72V36110 ⎯ 131,072 x 36.
- Higher density, 2Meg and 4Meg SuperSync II FIFOs.
- Up to 166 MHz Operation of the Clocks.
- User selectable Asynchronous read and/or write ports (PBGA Only).
- User selectable input and output port bus-sizing
- x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out.
- Big-Endian/Little-Endian user selectab.
