* DINOR (Divided bit-line NOR) architecture for the memory cell. Access Time Flash 85ns (Max.) 4M-bit SRAM is a 524,288 bytes / 262,144 words SRAM 85ns (Max.) asynchronous SRAM fabricated by silicon-gate CMOS technology. Supply Voltage VCC=2.7 ~ 3.6V The M6MGB/T321S4TP is a Stacked micro Multi Chip Pa
M6MGT321S4TP Datasheet (92.80 KB)
M6MGT321S4TP
92.80 KB
Cmos sram.
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Renesas LSIs
M6MGB/T321S4TP
33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS 3.3V-ONLY FLASH MEMORY & 4,.
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