M6MGT321S8TP Datasheet - Renesas

M6MGT321S8TP CMOS SRAM

M6MGB/T321S8TP provides for Software Lock Release function. Usually, all memory blocks are locked and can not be programed or erased, when F-WP# is low. Using Software Lock Release function, program or erase operation 32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words, can be excuted. 3.0V-.

M6MGT321S8TP Features

* DINOR (Divided bit-line NOR) architecture for the memory cell. Access Time Flash 85ns (Max.) 8M-bit SRAM is a 1,048,576 bytes / 524,288 words SRAM 85ns (Max.) asynchronous SRAM fabricated by silicon-gate CMOS technology. Supply Voltage VCC=2.7 ~ 3.0V The M6MGB/T321S8TP is a Stacked micro Multi Chip

M6MGT321S8TP_Renesas.pdf