MPC9773 Datasheet (Renesas) - LVCMOS PLL Clock Generator

MPC9773, LVCMOS PLL Clock Generator

The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock.

Normal operation of the MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.

The reference clock frequency and the divider for the feedba

MPC9773 Features

* 1:12 PLL based low-voltage clock generator

* 3.3 V power supply

* Internal power-on reset

* Generates clock signals up to 242.5 MHz

* Maximum output skew of 250 ps

* Differential PECL reference clock input

* Two LVCMOS PLL reference clock inp