* Low power consumption technology
* VDD = single power supply voltage of 2.4 to 5.5 V
* HALT mode
* STOP mode RL78 CPU core
* CISC architecture with 3-stage pipeline
* Minimum instruction execution time: Can be changed from high speed (0.0625 μs: @ 16 MHz operation with
R5F1214AASP Datasheet (1.78 MB)
R5F1214AASP
1.78 MB
Mcu.
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R01DS0431EJ0110 Rev.1.10
Aug 31, 2023
True low-power platform, 61-µA/MHz operating current, TA = 125°C operation, fr.
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