R5F51113ADLF Datasheet - Renesas

R5F51113ADLF 32 MHz 32-bit RX MCUs

* * * * * Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Ba.

R5F51113ADLF Features

* 32-bit RX CPU core

* 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz

* Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations

* Multiplication and division unit handles 32-bit × 32-bit operations (multiplication

R5F51113ADLF Datasheet (1.04 MB)