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R5F562TADDFF Datasheet - Renesas

R5F562TADDFF 100-MHz 32-bit RX MCUs

* Maximum operating frequency: 100MHz * 32-bit RX CPU * Minimum instruction execution time: One instruction per state (cycle of the system clock) * Address space: 4-Gbyte linear * Register set of the CPU * General purpose: Sixteen 32-bit registers * Control: Nine 32-bit r.

R5F562TADDFF Features

* 32-bit RX CPU core

* Max. operating frequency: 100 MHz Capable of 165 DMIPS in operation at 100 MHz

* Single precision 32-bit IEEE-754 floating point

* Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations

* Multiplication and division unit

R5F562TADDFF Datasheet (875.57 KB)