UPD48011318 Low Latency DRAM

Renesas

Description

μPD48011318 μPD48011336 1.1G-BIT Low Latency DRAM-III Common I/O Burst Length of 2 Datasheet R10DS0012EJ0200 Rev.2.00 Feb 01, 2013 .
The μPD48011318 is a 67,108,864-word by 18-bit and the μPD48011336 is a 33,554,432-word by 36-bit synchronous double data rate Low Latency RAM fabrica.

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Datasheet Specifications

Part number: UPD48011318
Manufacturer: Renesas ↗
File Size: 1.15 MB
Datasheet: UPD48011318-Renesas.pdf
Description: Low Latency DRAM

Features

* 1 cycle 600MHz DDR Muxed Address
* Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power
* Training sequence for per-bit deskew
* Selectable Refresh Mode: Auto or Overlapped Refresh
* Programmable PVT-compensated output i

Applications

* implementing error correction), excluding refresh overhead and data bus turn-around With a bus speed of 600 MHz, a burst length of 2, and a tRC of 13.3 ns, the Low Latency DRAM-III chip is capable of achieving this rate when accesses to at least 6 banks of memory are overlapped. These products are p

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UPD48011318 Low Latency DRAM Renesas

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