UPD48011318 Datasheet - Renesas

UPD48011318 Low Latency DRAM

The μPD48011318 is a 67,108,864-word by 18-bit and the μPD48011336 is a 33,554,432-word by 36-bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor eDRAM memory cell. The Low Latency DRAM-III chip is a 1.1Gbit DRAM capable of a sustained throu.

UPD48011318 Features

* 1 cycle 600MHz DDR Muxed Address

* Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power

* Training sequence for per-bit deskew

* Selectable Refresh Mode: Auto or Overlapped Refresh

* Programmable PVT-compensated output i

UPD48011318-Renesas.pdf