M54HC73 - DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
The M54/74HC73 is a high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated in silicon gate C2MOS technology.
It has the same high speed performance of LSTTL combined with true CMOS low power consumption.
Depending on the logic level applied to J and K inputs, this device changes state on the negat
M54HC73 M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR .
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HIGH SPEED fMAX = 75 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS73 B1R (Plastic Package) F1R (Ceramic Package)
