* The synchronous design allows a phase alignment between a clock and its data; this means a better BER (Bit Error Rate) performance. The advanced 0.35µm technology makes the STLVD112 suitable for data rates up to 200Mbit. The main application field is SDH/SONET telecom infrastructure. The STLVD112 f
STLVD112 Datasheet (151.24 KB)
STLVD112
151.24 KB
High speed protection switch.
www.DataSheet4U.com STLVD112 HIGH SPEED PROTECTION SWITCH s s s s s 24mA CMOS OUTPUT DRIVE CURRENT LVTTL INPUT THRESHOLDS CONTROLLED SKEW BETWEEN D.
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