* TER RESET (MR) sets all the control logic marker bits to ”0”. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. 8/12 HCC/HCF40105B Plastic DIP14 MECHANICAL DATA mm M
HCC40105B Datasheet (260.50 KB)
HCC40105B
260.50 KB
Fifo register.
HCC40105B HCF40105B FIFO REGISTER . . . . . . . . . . . INDEPENDENT ASYNCHRONOUS INPUTS AND OUTPUTS 3-STATE OUTPUTS EXPANDABLE IN EITHER DIRECTION S.
📁 Related Datasheet
HCC40100B 32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER (STMicroelectronics)
HCC40101B 9-BIT PARITY GENERATOR/CHECKER (STMicroelectronics)
HCC40102B 8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS (STMicroelectronics)
HCC40104B 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER (STMicroelectronics)
HCC40106B Rad-hard hex Schmitt trigger (STMicroelectronics)
HCC40107B DUAL 2-INPUT NAND BUFFER/DRIVER (STMicroelectronics)
HCC40108B 4 x 4 MULTIPORT REGISTER (STMicroelectronics)
HCC40109B Rad-hard quad lowto-high voltage level shifter (STMicroelectronics)
HCC4010B HEX BUFFER/CONVERTERS (STMicroelectronics)
HCC40110B DECADE UP-DOWN COUNTER/DECODER/LATCH/DRIVER (STMicroelectronics)
