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HCC4096B GATE J-K MASTER-SLAVE FLIP-FLOPS

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Description

HCC/HCF4095B HCC/HCF4096B GATE J-K MASTER-SLAVE FLIP-FLOPS *..16 MHz TOGGLE RATE (typ.) AT VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT .
OF B SERIES CMOS DEVICES” inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse.

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Applications

* T-type Flip-Flop D-type Flip-Flop Synchronous Binary Divide by Ten Counter STATE 0 1 2 3 4 5 6 7 8 9 QA 0 1 0 1 0 1 0 1 0 1 QB 0 0 1 1 0 0 1 1 0 0 QC 0 0 0 0 1 1 1 1 0 0 QD 0 0 0 0 0 0 0 0 1 1 NOTE: In all 4095B units the Set and Reset are Connected to VSS 7/13 HCC/HCF4095B HCC/HCF4096B WAV

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