K7D161874B Datasheet - Samsung Semiconductor

K7D161874B 512Kx36 & 1Mx18 SRAM

The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 524,288 words by 36 bits for K7D163674B and 1,048,576 words by 18 bits for K7D161874B, fabricated using Samsung's advanced CMOS technology. Single differential HSTL level clock, K and.

K7D163674B K7D161874B Document Title 16M DDR SYNCHRONOUS SRAM www.DataSheet4U.com 512Kx36 & 1Mx18 SRAM Revision History Rev No. Rev. 0.0 Rev. 0.1 History Initial document. Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS -to support 1.8~2.5V VDD, change some items. Change DC CHARACTERISTICS (Stop Clock Standby Current) -ISB1 : 100 -> 150 Change JTAG Instruction Cording - For Reserved Change DC CHARACTERISTICS (Increase Operating Current) - x36 : add 40mA, x18 : add 60mA Add DC CHARACTERIS.

K7D161874B Features

* 512Kx36 or 1Mx18 Organizations. 1.8~2.5V VDD/1.5V VDDQ.(1.9V max VDDQ) HSTL Input and Outputs. Single Differential HSTL Clock. Synchronous Pipeline Mode of Operation with Self-Timed Late Write.

* Free Running Active High and Active Low Echo Clock Output Pin.

* Asynchronous Output Ena

K7D161874B Datasheet (470.08 KB)