Description
K7D803671B K7D801871B Preliminary 256Kx36 & 512Kx18 SRAM Document Title 8M DDR SYNCHRONOUS SRAM Revision History Rev No.Rev.0.0 History -Initia.
Pin Name K, K SA
SA0, SA1 DQ VDD VDDQ VREF B1 B2 B3
Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (S.
Features
* 256Kx36 or 512Kx18 Organizations.
* 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).
* Programmable Impedance Output Drivers.
* Maximum Frequency : 333MHz (Data Rate : 666Mbps)
* 2.5V Core/1.5V Output Power Supply(2.0V max VDDQ).
* HSTL Input
