K7D803671B Datasheet (Samsung)

K7D803671B, SRAM

Pin Name K, K SA SA0, SA1 DQ VDD VDDQ VREF B1 B2 B3 Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (SA0 = LSB) Synchronous Data I/O Core Power Supply Output Power Supply HSTL Input Reference Voltage Load External Address Burst R/W Enable Single/Double

K7D803671B K7D801871B Preliminary 256Kx36 & 512Kx18 SRAM Document Title 8M DDR SYNCHRONOUS SRAM Revision History Rev No.

Rev.

0.0 History -Initial document.

Rev.

0.1 -ZQ tolerance changed from 10% to 15% Rev.

0.2 -Stop Clock Standby Current condition changed from VIN=VDD-0.2V or 0.2V fixed to VIN=VIH or VIH Rev.

0.3 -VDDQ Max.

changed to 2.0V SA0, SA1 defined for Boundary Scan Order Rev.

0.5 -Deleted -HC16 part(Part Number, Idd, AC Characterisctics) Rev.

0.6 - Absolute Maximum rati

K7D803671B Features

* 256Kx36 or 512Kx18 Organizations.

* 153(9x17) Pin Ball Grid Array Package(14mm x 22mm).

* Programmable Impedance Output Drivers.

* Maximum Frequency : 333MHz (Data Rate : 666Mbps)

* 2.5V Core/1.5V Output Power Supply(2.0V max VDDQ).

* HSTL Input