K4S560432B Datasheet - Samsung semiconductor

K4S560432B 256Mbit SDRAM 16M x 4bit x 4 Banks Synchronous DRAM LVTTL

The K4S560432B is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,785,216 words by 4 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock.

K4S560432B CMOS SDRAM 256Mbit SDRAM 16M x 4bit x 4 Banks Synchronous DRAM LVTTL Revision 0.2 May. 2000 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.2 May.2000 K4S560432B CMOS SDRAM Revision 0.1 (March 10, 2000) Deleted -80 Product Specification Changed the Current values of ICC5, ICC6 Changed tOH of -75 Product from 2.7ns to 3ns Changed the Bank select address in SIMPLIFIED TRUTH TABLE Note.

K4S560432B Features

* JEDEC standard 3.3V power supply

* LVTTL compatible with multiplexed address

* Four banks operation

* MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

* All inputs are

K4S560432B_Samsungsemiconductor.pdf