K4Y50024UC - (K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM

Product Overview

Samsung semiconductor

Part number	K4Y50024UC
Manufacturer	Samsung semiconductor
File Size	3.39 MB
Description	(K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM
Datasheet	K4Y50024UC Datasheet
Additional preview pages of the K4Y50024UC datasheet.

The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions.

Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling.
Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count.
On-chip termination - Adaptive impedance matching - Reduced system cost and routing complexity.
Highest sustained bandwidth per DRAM device - Up to 8000 MB/s sustained data rate - Eight banks : bank-interleaved transaction at full bandwidth - Dynamic request scheduling - Ear.

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Published: Mar 22, 2007 |