K4Y54044UF - XDR/RDRAM
XDR DRAM The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions.
There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.
The “N” appended to a signal name denotes the complem
www.DataSheet4U.com K4Y5416(/08/04)4UF XDR DRAM 256Mbit XDR DRAM(F-die) 2M x 16(/8/4) bit x 8s Banks Version 1.0 Jan.
2005 Version 1.0 Jan.
2005 Page -1 www.DataSheet4U.com K4Y5416(/08/04)4UF Change History Version 0.1( July 2004) - Preliminary - First Copy - Based on the Rambus XDR DRAMTM Datasheet Version 0.81 XDR DRAM Version 1.0( Jan.
2005) - Delete “Preliminary” - Based on the Rambus XDR DRAMTM Datasheet Version 0.85 Version 1.0 Jan.
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K4Y54044UF Features
* Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling
* Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count
* Programmable on-chip termination - Adaptive impedance matching - Reduced system cost
