The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions.
There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.
The “N” appended to a signal name denotes the complementary sign
www.DataSheet4U.com K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM 512Mbit XDR TM DRAM(C-die) Revision 1.1 August 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS
K4Y50084UC Features
* Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling
* Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count
* On-chip termination - Adaptive impedance matching - Reduced system cost and routing
K4Y50024UC_Samsungsemiconductor.pdf
Datasheet Details
K4Y50084UC, K4Y50024UC
Samsung semiconductor
3.39 MB
(k4y50024uc - k4y50164uc) 512mbit xdr tm dram.
This datasheet PDF includes multiple part numbers: K4Y50084UC, K4Y50024UC.
Please refer to the document for exact specifications by model.
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