K7I641882M Datasheet (Samsung semiconductor) - (K7I643682M / K7I641882M) 72Mb M-die DDRII SRAM Specification 165 FBGA

K7I641882M, (K7I643682M / K7I641882M) 72Mb M-die DDRII SRAM Specification 165 FBGA

Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input

K7I643682M K7I641882M 2Mx36 & 4Mx18 DDRII CIO b2 SRAM 72Mb M-die DDRII SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) www.DataSheet4U.com INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.

ALL INFORMATION IN THIS DOCUMENT IS PROVI

K7I641882M Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future freguency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.

* Pipelined, double-data rate operation.

* Common data input/output