K7I641884M Datasheet (Samsung semiconductor) - (K7I641884M / K7I643684M) 72Mb DDRII SRAM Specification

K7I641884M, (K7I641884M / K7I643684M) 72Mb DDRII SRAM Specification

Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input

K7I643684M K7I641884M 2Mx36 & 4Mx18 DDRII CIO b4 SRAM 72Mb DDRII SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) www.DataSheet4U.com INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

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K7I641884M Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future frequency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.

* Pipelined, double-data rate operation.

* Common data input/output