Description
K7I163682B K7I161882B Document Title 512Kx36 & 1Mx18 DDRII CIO b2 SRAM 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM Revision History Rev.No.0.0 0.1 H.
Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs Read, Wri.
Features
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future freguency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
* Pipelined, double-data rate operation.
* Common data input/output
