K7I163684B Datasheet - Samsung semiconductor

K7I163684B 512Kx36 & 1Mx18 DDRII CIO b4 SRAM

Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin, active when low Inpu.

K7I163684B K7I161884B 512Kx36 & 1Mx18 DDRII CIO b4 SRAM 18Mb DDRII SRAM Specification 165FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WI.

K7I163684B Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future frequency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.

* Pipelined, double-data rate operation.

* Common data input/output

K7I163684B_Samsungsemiconductor.pdf

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Datasheet Details

Part number:

K7I163684B

Manufacturer:

Samsung semiconductor

File Size:

454.90 KB

Description:

512kx36 & 1mx18 ddrii cio b4 sram.

K7I163684B Distributor

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K7I163684B K7I163684B 512Kx36 1Mx18 DDRII CIO SRAM Samsung semiconductor