K7I321882M Datasheet (Samsung semiconductor) - 1Mx36 & 2Mx18 DDRII CIO b2 SRAM

K7I321882M, 1Mx36 & 2Mx18 DDRII CIO b2 SRAM

Pin Name K, K SA SA0, SA1 DQ CQ, CQ B1 B2 B3 G LBO Pin Description Differential Clocks Synchronous Address Input Synchronous Burst Address Input (SA 0 = LSB) Synchronous Data I/O Differential Output Echo Clocks Load External Address Burst R/W Enable Single/Double Data Selection Asynchronous Output E

K7D803671B K7D801871B Document Title 8M DDR SYNCHRONOUS SRAM 256Kx36 & 512Kx18 SRAM Revision History Rev No.

Rev.

0.0 Rev.

0.1 Rev.

0.2 History -Initial document.

-ZQ tolerance changed from 10% to 15% -Stop Clock Standby Current condition changed from VIN=VDD-0.2V or 0.2V fixed to V IN =VIH or V IH -VDDQ Max.

changed to 2.0V SA0, SA1 defined for Boundary Scan Order -Deleted -HC16 part(Part Number, Idd, AC Characterisctics) - Absolute Maximum ratings VDDQ changed from 3.13V to 2.825V - LBO inpu

K7I321882M Features

* and the timing waveforms regarding the burst controllability. - Recommended DC operating conditions for Clock added. - AC test conditions for V DDQ=1.8V and Single ended clock added. (AC Test Conditions 2) - Package thermal characteristics added. - Add-HC35 part(Part Number, Idd, AC Characteristics)