K7J641882M Datasheet - Samsung semiconductor

K7J641882M (K7J641882M / K7J643682M) 72Mb M-die DDRII SRAM Specification

Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs 1 NOTE Q0-35 Data Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Refere.

K7J643682M K7J641882M www.DataSheet4U.com 2Mx36 & 4Mx18 DDR II SIO b2 SRAM 72Mb M-die DDRII SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVI.

K7J641882M Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future freguency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.

* Separate independent read and write data ports

* HSTL I/O

K7J641882M Datasheet (361.01 KB)

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Datasheet Details

Part number:

K7J641882M

Manufacturer:

Samsung semiconductor

File Size:

361.01 KB

Description:

(k7j641882m / k7j643682m) 72mb m-die ddrii sram specification.

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