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K7K3218U2C - 1Mx36 & 2Mx18 DDRII CIO b2 SRAM

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Datasheet Details

Part number
K7K3218U2C
Manufacturer
Samsung semiconductor
File Size
439.34 KB
Datasheet
download datasheet K7K3218U2C_Samsungsemiconductor.pdf
Description
1Mx36 & 2Mx18 DDRII CIO b2 SRAM

K7K3218U2C Product details

Description

Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply ( 1.8 V ) Output Power Supply ( 1.5V ) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output No Connect 2 1 NOTE R/W LD BW0, BW1,BW2, BW3 VREF Z

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