K7K1618T2C Datasheet - Samsung semiconductor

K7K1618T2C 512Kx36 & 1Mx18 DDRII CIO b2 SRAM

Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Contro.

K7K1636T2C K7K1618T2C 512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM 18Mb DDRII+ SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS.

K7K1618T2C Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future freguency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V

* Pipelined, double-data rate operation.

* Common data input/output bus .

* HSTL I/O

* Full dat

K7K1618T2C_Samsungsemiconductor.pdf

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Datasheet Details

Part number:

K7K1618T2C

Manufacturer:

Samsung semiconductor

File Size:

440.53 KB

Description:

512kx36 & 1mx18 ddrii cio b2 sram.

K7K1618T2C Distributor

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K7K1618T2C K7K1618T2C 512Kx36 1Mx18 DDRII CIO SRAM Samsung semiconductor