K7K1636U2C - 512Kx36 & 1Mx18 DDRII CIO b2 SRAM
Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Contro
K7K1636U2C K7K1618U2C 512Kx36 & 1Mx18 DDRII+ CIO b2 SRAM 18Mb DDRII+ SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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K7K1636U2C Features
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future freguency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V
* Pipelined, double-data rate operation.
* Common data input/output bus .
* HSTL I/O
* Full dat
