K7R320982C - (K7R32xx82C) QDR II b2 SRAM
Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Address Inputs Data Inputs 1 NOTE Q0-35 W R BW0, BW1,BW2, BW3 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC Data Outputs Write Control Pin, active when low Read Control Pin, active when low Block Write Control Pin, active whe
www.DataSheet4U.com K7R323682C K7R321882C K7R320982C 1Mx36 & 2Mx18 & 4Mx9 QDRTM II b2 SRAM 36Mb QDRII SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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ALL INFORMATION IN THIS DOCUME
K7R320982C Features
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future frequency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O.
* Separate independent read and write data ports with concurrent read and
