K7R320884M - 1M x 36 & 2M x 18 QDR II b4 SRAM
on page 2 and add HSTL I/O comment 0.3 1.
Update current characteristics in DC electrical characteristics 2.
Change AC timing characteristics 3.
Update JTAG instruction coding and diagrams 0.4 1.
Add -FC25 part(AC Characteristics) 2.
Add AC electrical characteristics.
3.
Change AC timing character
K7R323684M K7R321884M K7R320884M Preliminary 1Mx36 & 2Mx18 & 4Mx8 QDRTM II b4 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit QDRTM II b4 SRAM Revision History Rev.
No.
History 0.0 1.
Initial document.
0.1 1.
Package dimension modify.
P.20 from 13mmx15mm to 15mmx17mm 0.2 1.
Pin name change from DLL to Doff.
2.
Vddq range change from 1.5V to 1.5V~1.8V.
3.
Update JTAG test conditions.
4.
Reserved pin for high density name change from NC to Vss/SA 5.
Delete AC test condition about Clock
