K7S3218U4C Datasheet - Samsung semiconductor

K7S3218U4C - 1Mx36 & 2Mx18 QDR II b4 SRAM

Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs NOTE Q0-35 W R BW0, BW1,BW2, BW3 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC Notes: Data Outputs Write Control Pin,active when low Read Control Pin,active when low Block Write Control Pin,active when low Input Referenc.

K7S3236U4C K7S3218U4C 1Mx36 & 2Mx18 QDRTM II+ b4 SRAM 36Mb QDRII+ SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WI.

K7S3218U4C Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future frequency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V

* Separate independent read and write data ports with concurrent read and write operation

* HSTL I/O

K7S3218U4C_Samsungsemiconductor.pdf