S3P72F5 - The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrangeable M
Table 1 *1.
S3C72F5 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or output.
Individual pins are software configurable as opendrain or push-pull outpu
S3C72F5/P72F5 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVERVIEW The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, 8-bit and 16-bit timer/counter, and serial I/O, the S3C72F5 offers an excellent design solution for a wide variety of applications which require LCD functions.
Up to 39 pins of the 100-pin QFP package can be dedicated
S3P72F5 Features
* SUMMARY Memory
* 544 × 4-bit RAM (excluding LCD display RAM) 16,384 × 8-bit ROM Watch Timer
* Time interval generation: 0.5 s, 3.9 ms at 32768 Hz 4 frequency outputs to BUZ pin Clock source generation for LCD 39 I/O Pins
* I/O: 35 pins
