K7K3218U2C - 1Mx36 & 2Mx18 DDRII CIO b2 SRAM

Samsung semiconductor

K7K3218U2C Datasheet Preview — Preview of K7K3218U2C PDF

Datasheet Details

Part number	K7K3218U2C
Manufacturer	Samsung semiconductor
File Size	439.34 KB
Description	1Mx36 & 2Mx18 DDRII CIO b2 SRAM
Datasheet	K7K3218U2C_Samsungsemiconductor.pdf

K7K3218U2C Product details

Description

Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply ( 1.8 V ) Output Power Supply ( 1.5V ) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output No Connect 2 1 NOTE R/W LD BW0, BW1,BW2, BW3 VREF Z

Features

1.8V+0.1V/-0.1V Power Supply.
DLL circuitry for wide output data valid window and future freguency scaling.
I/O Supply Voltage 1.5V+0.1V/-0.1V.
Pipelined, double-data rate operation.
Common data input/output bus.
HSTL I/O.
Full data coherency, providing most current data.
Synchronous pipeline read with self timed late write.
Read latency : 2.5 clock cycles.
Registered address, control and data input.

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Published: Apr 19, 2011 |