CY2SSTV16859 Datasheet (SpectraLinear) - 13-Bit to 26-Bit Registered Buffer

CY2SSTV16859, 13-Bit to 26-Bit Registered Buffer

This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations.

All inputs are compatible with the JEDEC Standard for SSTL-2, except the LVCMOS reset (RESET#) input.

All outputs are SSTL_2, Class II compatible.

Block Diagram Pin Configuration RESET # CLK CLK # D1 D VREF C Q1B

CY2SSTV16859 Features

* Differential clock inputs up to 280 MHz

* Supports LVTTL switching levels on the RESET# pin

* Output drivers have controlled edge rates, so no external resistors are required. www.DataSheet4U.com The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequen