A3R12E40CBF, A3R12E30CBF Datasheet - Zentel

A3R12E40CBF - 512Mb DDRII Synchronous DRAM

A3R12E30CBF A3R12E40CBF 512Mb DDRII Synchronous DRAM 512Mb DDRII SDRAM Specification A3R12E30CBF A3R12E40CBF Zentel Electronics Corp. Revision 1.2 Sep., 2013 A3R12E30CBF A3R12E40CBF 512Mb DDRII Synchronous DRAM Specifications Density: 512M bits Organization ⎯ 16M words × 8 bits × 4 banks (A3R12E30CBF) ⎯ 8M words × 16 bits × 4 banks (A3R12E40CBF) Package ⎯ 60-ball FBGA(μBGA) (A3R12E30CBF) ⎯ 84-ball FBGA(μBGA) (A3R12E40CBF) ⎯ Lead-free (RoHS compliant) .

A3R12E40CBF Features

* Double-data-rate architecture; two data transfers per clock cycle

* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture

* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re

A3R12E30CBF-Zentel.pdf