A3R1GE4EGF Datasheet - Zentel

A3R1GE4EGF 1Gb DDRII SDRAM

A3R1GE4EGF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specification A3R1GE4EGF Zentel Electronics Corp. Revision 1.0 Apr., 2010 Specifications Density: 1G bits Organization ⎯ 8M words × 16 bits × 8 banks (A3R1GE4EGF) Package ⎯ 84-ball FBGA(μBGA) (A3R1GE4EGF) ⎯ Lead-free (RoHS compliant) Power supply: VDD, VDDQ = 1.8V ± 0.1V Data rate: 800Mbps/667Mbps (max.) ⎯ 800Μbps/667Mbps(max) 2KB page size (A3R1GE4EGF) ⎯ Row address: A0 to A12 ⎯.

A3R1GE4EGF Features

* Double-data-rate architecture; two data transfers per clock cycle

* The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture

* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re

A3R1GE4EGF Datasheet (1.64 MB)