A3V28S40JTP Datasheet - Zentel

A3V28S40JTP 128M Single Data Rate Synchronous DRAM

A3V28S40JTP is organized as 4-bank x 2,097,154-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. A3V28S40JTP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.

A3V28S40JTP Features

* - Single 3.3V ±0.3V power supply - Maximum clock frequency : - 60:166MHz/-70:143MHz/-75:133MHz - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (pr

A3V28S40JTP-Zentel.pdf