A3V56S40GTP Datasheet - Zentel

A3V56S40GTP 256M Single Data Rate Synchronous DRAM

A3V56S30GTP is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and A3V56S40GTP is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK. A3V56S30GTP and A3V56S40GTP achieve very high speed data rates up to 16.

A3V56S40GTP Features

* - Single 3.3V ±0.3V power supply - Maximum clock frequency: -60:166MHz/-70:143MHz/-75:133MHz - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0, BA1 (Bank Address) - CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (progr

A3V56S40GTP Datasheet (0.99 MB)