74AC11534
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Octal d-type edge-triggered flip-flops. 54AC11534 . . . JT PACKAGE 74AC11534 . . . DW OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 1
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74AC11520 - 8-BIT IDENTITY COMPARATOR
(Texas Instruments)
74AC11520 8-BIT IDENTITY COMPARATOR
D Compares Two 8-Bit Words D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPICt (E.
74AC11521 - 8-BIT IDENTITY COMPARATORS
(Texas Instruments)
54AC11521, 74AC11521 8-BIT IDENTITY COMPARATORS
• Compares Two 8-Bit Words • Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND .
74AC11590 - 8-BIT BINARY COUNTER
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• Parallel Registered Outputs • Internal Counters Have Direct Clear • Flow-Through Architecture Optimizes
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74AC11593 - 8-BIT BINARY COUNTER
(Texas Instruments)
• Parallel 3-State I/O: Register Inputs/
Counter Outputs
• Counter Has Direct Overriding Load and
Clear
• Flow-Through Architecture Optimizes
PCB Layo.
74AC11 - TRIPLE 3-INPUT AND GATE
(STMicroelectronics)
..net
74AC11
TRIPLE 3-INPUT AND GATE
PRELIMINARY DATA
s s
s
s
s
s
s
s
s
HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V LOW POWER DIS.
74AC11 - Triple 3-Input AND Gate
(Fairchild Semiconductor)
74AC11 — Triple 3-Input AND Gate
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Features
■ ICC reduced by 50% ■ Outputs source/sink 24mA
January 2008
General Descri.
74AC11000 - QUADRUPLE 2-INPUT POSITIVE-NAND GATE
(Texas Instruments)
.ti.
FEATURES
• Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
• EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Pro.
74AC11002 - QUADRUPLE 2-INPUT POSITIVE-NOR GATES
(Texas Instruments)
54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND Configuration
Min.
74AC11004 - HEX INVERTER
(Texas Instruments)
74AC11004 HEX INVERTER
D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
D.
74AC11008 - QUADRUPLE 2-INPUT POSITIVE-AND GATE
(Texas Instruments)
74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE
D Flow-Through Architecture Optimizes
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Minimize High-.
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