CDCF2509 Datasheet - Texas Instruments

CDCF2509 3.3-V Phase-Lock Loop Clock Driver

The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates.

CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C APRIL 1999 REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for this Device D Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 D Spread Spectrum Clock Compatible D Operating Frequency 25 MHz to 140 MHz D Static Phase Error Distribution at 66 MHz to 133 MHz is ±125 ps D Jitter (cyc cyc) at 66 MHz to 133 MHz Is |70| ps D Available in Plastic 24-Pin TSSOP D Phase-Lock Loop Clock Distributio.

CDCF2509 Datasheet (501.99 KB)